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Preliminary
(R)
DR5001 868.35 MHz Receiver Module
* * * *
Designed for Short-Range Wireless Data Communications Supports up to 19.2 kbps Encoded Data Transmissions 3 V, Low Current Operation plus Sleep Mode Ready to Use OEM Module
The DR5001 receiver module is ideal for short-range wireless data applications where robust operation, small size and low power consumption are required. The DR5001 utilizes RFM's RX6001 amplifiersequenced hybrid (ASH) architecture to achieve this unique blend of characteristics. The receiver RX6001 is sensitive and stable. A wide dynamic range log detector provides robust performance in the presence of onchannel interference or noise. Two stages of SAW filtering provide excellent receiver out-of -band rejection. The DR5001 includes the RX6001 plus all configuration components in a ready-to-use PCB assembly excellent for prototyping and intermediate volume production runs.
Absolute Maximum Ratings Rating
Power Supply and All Input/Output Pins Non-Operating Case Temperature Soldering Temperature (10 seconds)
Value
-0.3 to +4.0 -50 to +100 230
Units
V C C
Electrical Characteristics, 2.4 kbps On-Off Keyed
Characteristic Operating Frequency Modulation Type Data Rate Receiver Performance (OOK @ 2.4 kbps) Input Current, 3 Vdc Supply Input Signal for 10-4 Rejection, 30 MHz Sleep Mode Current Power Supply Voltage Range Operating Ambient Temperature BER, 25 C RREJ tSR IS VCC TA 2.7 -20 3 55 200 5 3.5 +65 IR -100 1.8 mA dBm dB s A Vdc C Sym fO Notes Minimum 868.15 OOK 2.4 19.2 kbps Typical Maximum 868.55 Units MHz
Sleep to Receive Switch Time(100 ms sleep, -85 dBm signal)
DR5001 Pin Out
RF GND 14 AGC/VCC PK DET RX BBO RX DATA NC 1 2 3 4 5 6 GND 7 GND
DR5000 Pin Out
RFIO 13 12 11 10 9 8 CTR0
DR5001 Outline Drawing DR5000 Outline Drawing
.70 .25 .20 .165 .10
CTR1 GND VCC LPF ADJ
.70
Dimensions in inches
RF Monolithics, Inc. Phone: (972) 233-2903 Fax: (972) 387-8148 RFM Europe Phone: 44 1963 251383 Fax: 44 1963 251510 (c)1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
E-mail: info@rfm.com http://www.rfm.com DR5001-081203
Page 1 of 4
868.35 MHz
Pin Desciptions Pin Name
Receiver Module
Description
This pin is connected directly to the receiver AGCCAP pin. To disable AGC operation, this pin is tied to VCC. To enable AGC operation, a capacitor is placed between this pin and ground. This pin controls the AGC reset operation. A capacitor between this pin and ground sets the minimum time the AGC will hold-in once it is engaged. The hold-in time is set to avoid AGC chattering. For a given hold-in time tAGH, the capacitor value CAGC is: CAGC = 19.1* tAGH, where tAGH is in s and CAGC is in pF A 10% ceramic capacitor should be used at this pin. The value of CAGC given above provides a hold-in time between tAGH and 2.65* tAGH, depending on operating voltage, temperature, etc. The hold-in time is chosen to allow the AGC to ride through the longest run of zero bits that can occur in a received data stream. The AGC hold-in time can be greater than the peak detector decay time, as discussed below. However, the AGC hold-in time should not be set too long, or the receiver will be slow in returning to full sensitivity once the AGC is engaged by noise or interference. The use of AGC is optional when using OOK modulation with data pulses of at least 30 s. Active or latched AGC operation is required for ASK modulation and/or for data pulses of less than 30 s. The AGC can be latched ON once engaged by connecting a 150 K resistor between this pin and ground, instead of a capacitor. AGC operation depends on a functioning peak detector, as discussed below. The AGC capacitor is discharged in the receiver power-down (sleep) mode. Note that provisions are made on the circuit board to install a jumper between this pin and the junction of C2 and L3. Installing the jumper allows either this pin or Pin 9 to be used for the Vcc supply when AGC operation is not required. This pin is connected directly to the receiver PKDET pin. This pin controls the peak detector operation. A capacitor between this pin and ground sets the peak detector attack and decay times, which have a fixed 1:1000 ratio. For most applications, the attack time constant should be set to 6.4 ms with a 0.027 F capacitor to ground. (This matches the peak detector decay time constant to the time constant of the 0.1 F coupling capacitor C3.) A 10% ceramic capacitor should be used at this pin. The peak detector is used to drive the "dB-below-peak" data slicer and the AGC release function. The AGC hold-in time can be extended beyond the peak detector decay time with the AGC capacitor, as discussed above. Where low data rates and OOK modulation are used, the "dB-below-peak" data slicer and the AGC are optional. In this case, the PKDET pin can be left unconnected, and the AGC pin can be connected to VCC to reduce the number of external components needed. The peak detector capacitor is discharged in the receiver power-down (sleep) mode. See the description of Pin 3 below for further information. This pin is connected directly to the receiver BBOUT pin. On the circuit board, BBOUT also drives the receiver CMPIN pin through C3, a 0.1 F coupling capacitor (tBBC = 6.4 ms). RX BBO can also be used to drive an external data recovery process (DSP, etc.). The nominal output impedance of this pin is 1 K. The RX BBO signal changes about 10 mV/dB, with a peak-to-peak signal level of up to 675 mV. The signal at RX BBO is riding on a 1.1 Vdc value that varies somewhat with supply voltage and temperature, so it should be coupled through a capacitor to an external load. A load impedance of 50 K to 500 K in parallel with no more than 10 pF is recommended. Note the AGC reset function is driven by the signal applied to CMPIN through C3. When the receiver is in power-down (sleep) the output impedance of this pin becomes very high, preserving the charge on the coupling capacitor(s). The value of C3 on the circuit board has been chosen to match typical data encoding schemes at 2.4 kbps. If C3 is modified to support higher data rates and/or different data encoding schemes and PK DET is being used, make the value of the peak detector capacitor about 1/3 the value of C3. RX DATA is connected directly to the receiver data output pin, RXDATA. This pin will drive a 10 pF, 500 K parallel load. The peak current available from this pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) or receive mode, this pin becomes high impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite logic state when this pin is high impedance (do not connect the pull-up resistor to a supply voltage higher than 3.5 Vdc or the receiver will be damaged). This pin must be buffered to successfully drive low-impedance loads.
1
AGC/VCC
2
PK DET
3
RX BBO
4
RX DATA
5 6, 7
NC GND
RF Monolithics, Inc. Phone: (972) 233-2903 Fax: (972) 387-8148 RFM Europe Phone: 44 1963 251383 Fax: 44 1963 251510 (c)1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
E-mail: info@rfm.com http://www.rfm.com DR5001-081203
Page 2 of 4
868.35 MHz
Receiver Module
This pin is the receiver low-pass filter bandwidth adjust, and is connected directly to the receiver LPFADJ pin. R6 on the circuit board (330 K) is connected between LPFADJ and ground will be in parallel with any external resistor connected to LPF ADJ. The filter bandwidth is set by the parallel resistance of R6 and the external resistor (if used). The equivalent resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth fLPF from 4.4 kHz to 1.8 MHz. The 3 dB filter bandwidth is determined by: fLPF = 1445/ (330*RLPF/(330 + RLPF)), where RLPF is in kilohms, and fLPF is in kHz 8 LPF ADJ A 5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between fLPF and 1.3* fLPF with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase response. The peak drive current available from RXDATA increases in proportion to the filter bandwidth setting. As shipped, the receiver module is set up for nominal 2.4 kbps operation. An external resistor can be added between Pin 8 and ground to support higher data rates. Preamble training times will not be decreased, however, unless C3 is replaced with a smaller capacitor value (see the descriptions of Pins 2 and 3 above). Refer to sections 1.4.3, 2.5.1 and 2.6.1 in the ASH Transceiver Designer's Guide for additional information on data rate adjustments. 9 10 VCC GND This is the positive supply voltage pin for the module. The operating voltage range is 2.7 to 3.5 Vdc. It is also possible to use Pin 1 as the Vcc input. Please refer to the Pin 1 description above. This is the supply voltage return pin. CTR1 is connected to the CNTRL1 control pin on the receiver. CTR1 and CTR0 select the transceiver operating modes. CTR1 and CTR0 both high place the unit in the receive mode. CTR1 and CTR0 both low place the unit in the power-down (sleep) mode. CTR1 is a high-impedance input (CMOS compatible). This pin must be held at a logic level; it cannot be left unconnected. At turn on, the voltage on this pin and CTR0 should rise with VCC until VCC reaches 2.7 Vdc (receive mode). Thereafter, any mode can be selected. CTR0 is connected to the CNTRL0 control pin on the receiver CTR0 is used with CTR1 to control the operating modes of the receiver. CTR0 is a high-impedance input (CMOS compatible). This pin must be held at a logic level; it cannot be left unconnected. At turn on, the voltage on this pin and CTR1 should rise with VCC until VCC reaches 2.7 Vdc (receive mode). Thereafter, any mode can be selected. RFIO is the RF input/output pin. A matching circuit for a 50 ohm load (antenna) is implemented on the circuit board between this pin and the receiver SAW filter transducer. This pin is the RF ground (return) to be used in conjunction with the RFIO pin. For example, when connecting the transceiver module to an external antenna, the coaxial cable ground is connected this pin and the coaxial cable center conductor is connected to RFIO.
11
CTR1
12
CTR0
13
RFIO
14
RF GND
2.4 kbps Application Circuit
19.2 kbps Application Circuit
3 Vdc
3 Vdc
12 13 14 1
11
10
9
8 7 6
12 13 14 1
11
10
9
8 7 6 33 k
DR5001 DR3000
2 3 4 5
DR5001
2 3 4 5
Data Out
Data Out
RF Monolithics, Inc. Phone: (972) 233-2903 Fax: (972) 387-8148 RFM Europe Phone: 44 1963 251383 Fax: 44 1963 251510 (c)1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
E-mail: info@rfm.com http://www.rfm.com DR5001-081203
Page 3 of 4
868.35 MHz
Receiver Module
RFIO (13)
RF GND (14)
DR5001 Schematic
CTR0 (12) CTR1 (11) VCC (9) + C4 C5 R8 R1 R2 R3
20 L1 C1 L2 1
11
ASH Receiver
10
R4
LPF ADJ (8) C3 R6 C2 GND (6, 7, 10)
RX BBO (3) AGC/VCC (1) PK DET (2) RX DATA (4)
Note: Preliminary specifications, subject to change without notice.
RF Monolithics, Inc. Phone: (972) 233-2903 Fax: (972) 387-8148 RFM Europe Phone: 44 1963 251383 Fax: 44 1963 251510 (c)1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
E-mail: info@rfm.com http://www.rfm.com DR5001-081203
Page 4 of 4

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